资源列表
digi_cpld_lcd
- Digital clock implementation using VHDL-Digital clock implementation using VHDL
LCD_BY_CPLD
- LCD Interfacing Code using CPLD
lift_contr_ssd
- Lift controller using seven segment display
SSD_MULTIPLEXING
- four seven segment displays are in multiplexing implemented on xilinx FPGA XC3S50
step_mot_wave_drive
- Stepper motor wave drive logic using vhdl implemented on fpga board
tlc_work_9
- Traffic light controller a four way logic implemented using cpld
EQctrl_20b_edge
- verilog edge type DFE
i2cSlave
- i2c communication slave module
serialInterface
- verilog i2c serial interface module
uart_fifo
- FPGA模拟UART,实现对自发自收. -simulating interface of uart on the fpga
DC_motor
- 为一个直流电机驱动控制程序，包括两个子模块和一个顶层模块，均为verilog源码。-A dc motor drive control code, including two modules and a top-level module, they are all the verilog code.
verilogiic1121
- 用verilog状态机写的IIC通信模块，包括两个子模块和一个顶层模块，均为verilog源码-Written in verilog state machine IIC communication module, including two modules and a top-level module, they are all the verilog code.