资源列表
Ch9
- 《Verilog HDL数字系统设计及仿真》第九章常见功能电路的HDL模型源代码-" Verilog HDL design and simulation of digital systems," Chapter IX common functional circuits HDL model source code
Ch10
- 《Verilog HDL数字系统设计及仿真》第十章完整的设计实例源代码-" Verilog HDL design and simulation of digital systems," Chapter complete design example source code
a_vhd_16550_uart
- 串口模块，带APB接口的。挂载APB总线上可以直接利用。-UART module with APB
sdram
- verilog sdram读写控制，实现数据存储于发送-sdram read and write，data store and communication
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
SDH
- SDH vhdl实现-SDH VHDL
tel
- 电话用户信令控制器的VHDL实现-Telephone subscriber signaling controller based on VHDL
PCM
- PCM码流时隙信号产生模块的VHDL实现-PCM stream slot signal generation module based on VHDL
decoder
- 七段译码器的VHDL实现-The seven segment decoder implementations of VHDL
check
- 11100 码流检测模块的VHDL实现- 11100 stream detection module based on VHDL
counter
- 异步复位的十进制计数器-Decade counter with asynchronous reset