资源列表
VerilogHDL_design_rule
- 自己在设计中的总结的设计要点，其中经历了几个项目，把其中的心得里路在其中，希望对各位同学和同事有帮助-Themselves in the design summary of the design features, which has gone through several projects, which experience the mile in which you want to help students and colleagues
Mul
- VHDL乘法器 四输入 四输出的代码设计-VHDL multiplier four input four-output code design
plj
- 基于VHDL的简易数字频率计，具体功能不清楚请大家验证！ -Simple VHDL-based digital frequency meter, the specific function is not clear please verify!
qingdaqi
- 四路抢答器，超时报警，提前抢答报警，计分等-Answer four, and overtime alarm, warning in advance Answer, including classification
fifos
- 通用的ｆｉｆｏ设计，带有ｔｅｓｔｂｅｎｃｈ，和ｄｅｓｉｇｎ＿ｆｌｏｗ-Fifo generic design, with a testbench, and design_flow
conditioner
- 空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd-Air-conditioning systems finite state automata encoding, various sources described in order to compile conditioner.vhd, conditioner_stim.vhd
TLC
- 交通灯控制器编码，源描述的编译顺序tlc.vhd，est_vector.vhd-Traffic lights controller code, the source described in order to compile tlc.vhd, est_vector.vhd
gcd_disp
- 最大公约数七段显示器编码,各个源描述的编译顺序gcd_disp.vhd,vhdl.vhd,stim.vhd-Seven-Segment Display common denominator coding, various sources described in order to compile gcd_disp.vhd, vhdl.vhd, stim.vhd
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
logicassign
- 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd-The same base type to distinguish the two types of assignment compatibility issues, the various sources described in the order of the compiler: logic.vhd, assign.vhd
ddr_dimm
- 256Mb_ddr 实现ddr_dimm操作-256Mb_ddr achieve ddr_dimm operation
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench