资源列表
Zynq-7000-for-Software-Engineers
- Zynq-7000软件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Software Engineers
SPI_ROM
- FPGA实现非标准SPI总线数据的接收和解码，并实现ROM数据的读取和执行-FPGA implementation of non-standard SPI bus to receive and decode the data, and to achieve ROM data read and
rec
- 8点8位的FFT，verilog语言，经过Quartus仿真验证-8 piont 8 bits of FFT, verilog language, through the Quartus simulation
shuzizhong
- 基于basys2的简易数字钟，包含校时功能-A simple digital clock base on basys2 board, including timing function.
Additionneur_ise12migration
- additionneur code vhdl for fpga-additionneur code vhdl for fpga
multiplexuer_ise12migration
- multiplixeur vhdl code for fpga-multiplixeur vhdl code for fpga
Clock
- 该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。-The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules.
sequence
- 序列仿真器，VHDL描述完成对状态机的模拟-Sequence simulator, VHDL descr iption to complete the state machine simulation
carsys
- 倒车雷达，可以完成在3米以内的测距并发出不同的警报声-Reversing radar, can be completed in less than 3 meters distance and send different alert sound
anjian2
- 实现LED流水灯 按键功能 暂停 点灭-Implement LED water lights Key Function Pause blinking
ClockQUARTUSVHDL
- 12/24小时数字时钟VHDL设计 包括顶层文件的设计和VHDL源程序-12/24 hour digital clock design, including the top-level VHDL design and VHDL source code file
Signal-Generator-VHDL-design
- 信号发生器VHDL设计 波形可选：正弦(sine)，方波(sqr)，锯齿波(jc_de和jc_in两种)，三角波(sanj)和阶梯波(stair)信号模块-Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) sig