资源列表
Song-playback-circuit-design-VHDL
- 乐曲播放电路VHDL设计 附仿真报告、顶层文件和源程序-Song playback circuit design VHDL simulation report attached, and the top-level source file
CPUver2
- 这是一个有关单周期CPU设计的一个参考，里面顶层模块已经写好，而其他模块的内容则是以注释的形式存在，如果要跑这个代码的话，把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。- 翻译关闭即时翻译 英语 中文 德语 检测语言 中文(简体) 英语
timecounter60sandpause
- 计时器数码管做到60s计数，外接键盘按键暂停-Digital timer 60s do count, an external keyboard to pause
Divisor_Frec
- Code in vhdl of divisor of frequency in FPGA
cronometro1.c
- cronometro atmel 328p code vision avr
EPD
- Quartus II开发环境下的鉴相器的图形实现。-Quartus II phase discriminator
ARM(Verilog-a-VHDL)
- 基于VHDL/Verilog实现的arm0,ARM5-7核-Based on VHDL/Verilog implementations arm0, ARM5-7 nuclear
Simple-design-of-traffic-lights
- 交通灯的显示有很多方式，如十字路口、丁字路口等，而对于同一个路口又有很多不同的显示要求，比如十字路口，车子如果只要东西和南北方向通行就很简单，而如果车子可以左右转弯的通行就比较复杂，本实验仅针对最简单的南北和东西直行的情况。-Traffic lights show there are many ways, such as intersections, T-junction, etc., and for the same intersection there are a lot of differ
Multiplier
- 设计一个能进行两个十进制数相乘的乘法器，乘数和被乘数均小于100。-Can design a multiplier multiplying two decimal numbers, the multiplier and multiplicand are less than 100.
DEMUX1_4
- this project about demultiplexer one to four compiled and implanted in cart fpga xilinx 3E, with file .bit
MUX4_1_2bits_fonction
- this project about multiplexer four to one compiled and implanted in cart fpga xilinx 3E, with file .bit
m_counter
- this project about compteur m bit compiled and implanted in cart fpga xilinx 3E, with file .HDL and .bit