资源列表
_Modelsim
- modelsim仿真软件使用的参考基本例程-modelsim reference software routines
estruct
- Ejemplo sencillo de encender un led en VHDL
f1
- 简单的宽脉冲状态同步机，输入信号通过两个D触发器到输出。附仿真结果图。-Synchronizer to deal with wide pulse signal.
fh2
- 窄脉冲状态同步机，输入信号通过三个D触发器到达输出端口。-Syhchronizer to deal with narrow pulse signal.
tcd1206
- tcd1206的verilog 驱动，已测试通过，需要的可以相互学习借鉴一下-the driver of tcd1206d(verilog),which had been tested
ethernet
- opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
stopwatch
- 在FPGA上实现秒表，有分秒毫秒三中不同显示。仅供参考，不算优质的代码-Realize stopwatch on FPGA, minutes and seconds there are three different display milliseconds. For reference only, not the quality of the code
led_flash
- 一个简单的流水灯设计，适用于Verilog入门的同学，练习如何进行简单的硬件语言描述-A simple water lamps designed for Verilog entry students practice how to make simple hardware descr iption language
my_alu
- 一个简单的ALU程序设计，实现以下功能： 逻辑运算：与、或、非、异或、逻辑左移、逻辑右移 算术运算：加、减 -A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction
Serial_Adder
- 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder
time_test
- 利用10M的时钟，设计一个单周期形状的周期波形。这是用Verilog写的-Use 10M clock cycle design a single cycle waveform shape. This is written in Verilog
XC3S400TQ144
- Just little program for xilinx FPGA. It is can be used as a example for education.