资源列表
sram_controller
- 国外网站上面找到的sram_controller，可借鉴性很强。可以扩展数据和地址宽度。-Foreign sites found above sram_controller, can draw on strong. Can extend the width of the data and address.
DE2_NIOS_LITE_SRAM
- DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
fftshixian
- OFDM系统中FFT的Verilog HDL 语言实现。-OFDM system FFT of Verilog HDL language.
FPGA
- 这些课件可以作为对FPGA有兴趣的人学习的入门资料，包含EDA的概述、FPGA结构与配置、VHDL语言、QuartusII软件、SOPC和NIosII嵌入式处理器设计、DSP Builder系统设计工具等内容-These courseware on the FPGA can be used as those who are interested in learning introductory information, including EDA overview, FPGA structure
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
DDR2Controller
- DDR2 Controller DDR2 Controller
SlidesforVHDL
- VHDL语言及其应用,一共76页，非常不错的资料，为大家分享！-VHDL language and its applications, a total of 76, very good information to share with you!
scan_keyboard
- 读取4*4键盘的键值，并用数码管显示，我写的，值得下载！-Read 4* 4 keyboard keys, and digital display, I wrote, it is worth downloading!
clock
- 可以实现时间调节，十二，二十四小时转换，定时，闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
xiaodou
- 一个键盘的消抖动电路。采用了硬件形式的，同时也键入了微分环节，可以将输出的脉冲降为一个时钟周期。-A keyboard eliminate jitter circuit. Used forms of hardware, but also type of differential link pulse output can be reduced to one clock cycle.
erwertwerwe
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
sdfsugfus
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing