资源列表
VHDL
- 7段数码显示译码器设计，包裹程序设计，实验目的，内容，图像。-7 digital display decoder design, package design, experimental purposes, content, images.
(Mealy)
- 状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能-The basis of state machine to achieve a state of transition between the four different situations in the state of the conversion function
S_MACHINE
- 状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能-The basis of state machine to achieve a state of transition between the four different situations in the state of the conversion function
3_8_decoder
- 利用CASE语句的3-8译码器,3个为数据输入,3个为控制端,分别为S1,S2,S3,输出数据为八位-Use CASE statement 3-8 decoder, three for data entry, three for the control side, namely S1, S2, S3, output data for eight
RL_SHIFT
- 带有同步预置的加载左右移位寄存器VHDL源代码-With synchronous preset load shift register about VHDL source code
led
- LED显示功能，使用VHDL语言编程，基于FPGA-LED display, the use of VHDL language programming, based on FPGA
vhdl
- 着个是一个8051的完整源代码，用VHDL书写。需要的可以看看，很有好处-8051 a month is a complete source code, written using VHDL. Needs can see, it is beneficial to
RS_204_188_decoder
- 使用verilog完成了RS编码的设计，编码参数为输入188，输出204-The use of Verilog coding RS completed the design, coding parameters for the importation of 188, the output 204
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
yueqvyanzou
- 基于MUXPLUS2的VHDL程序，实现音乐播放，-MUXPLUS2 the VHDL-based procedures, the realization of music player,
modelsimshiyong
- modelsim的详细开发和使用过程 适合初级modelsim学员-ModelSim detailed process of development and use of ModelSim for primary students
Modelsim
- modelsim 的使用具体方法与步骤 以及与Quartus联合仿真-ModelSim the use of specific methods and procedures, as well as a joint simulation with the Quartus