资源列表
write_rd
- 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
select_32
- 32位 2选1 选择器 VHDL语言程序-32 2 election 1 selector VHDL Language Program
write_io
- DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
rs1_7seg_pci-0.0.1.tar
- Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd. -Raggedstone1 IP core.Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
tony_wu
- Verilog HDL程序 Verilog HDL程序-Verilog HDL procedural procedures Verilog HDL
asfpga_v1.00e.tar
- asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set.
uart_regs
- UART串行通讯FPGA实现，新手上道请多多指教-FPGA realization of UART serial communication, and newcomers on the Road, please advice
2
- 里面有四个vhdl源程序 分别为状态机 三位表决器 和交通灯 优先编码器-There are four VHDL source code for the state machine, respectively, the three voting machines and traffic lights priority encoder
some_examples_of_vhdl_language
- 主要关于一些fpga的编程实例，有一些用处-Mainly on the number of FPGA programming examples, there are some useful
VHDL
- VHDL基础的编程源代码，对初学者很有参考价值-VHDL-based programming source code, useful reference for beginners
fifo_src
- verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.