资源列表
xapp336_8b10b
- 8b10b reference design
tSinCordic
- 是codic算法实现Sin的浮点C程序，包括定点和浮点程序，已经通过验证.-Sin is codic floating-point algorithm C procedures, including fixed-point and floating-point procedures, has been validated.
vhdl
- 基于VHDL的POC编写与实现 实现三次握手-VHDL-based preparation and implementation of the POC to achieve three-way handshake
polar2rect_VHDL
- 是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd-Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cord
poc1
- poc的VHDL详细设计 实现握手信号的交互 -poc of VHDL handshake signal to achieve the detailed design of interactive
cpu
- cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
multiply
- 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
cordiccos
- 改进的cordic算法的迭代cos结构，适用于altera。-Improved Iterative CORDIC algorithm cos structure, applicable to altera.
DCT2IDCT2
- CT2 IDCT2 变换C代码。经调试成功，适用于altera,有结果。-CT2 IDCT2 transform C code. After successful testing for altera, bear fruit.
run_watch
- 提供一个数字秒表的EDA设计实例，内故有VHDL源代码，并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
ask
- 提供一个把通信中ASK调制用VHDL来实现的例子，内附有相应的VHDL源程序。-To provide a communication ASK modulation achieved using VHDL example, enclosing a corresponding VHDL source code.