资源列表
Verilog
- verilog硬件语义的介绍，里面囊括了几乎所有verilog的相关硬件的语义。-Verilog hardware semantics introduced, which include almost all the relevant hardware Verilog semantics.
fpgaexperience
- 很不错的FPGA设计学习资料。非常值得看一看哦。-FPGA design is very good learning materials. Oh well worth a look.
vhdl100
- VHDL的大量实用例子，一共有100个哦-VHDL of a large number of practical examples, a total of 100 Oh
vhdl
- VHDL源码-VHDL source
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
292548
- < FPGA数字电子系统设计与开发实例导航>>的源代码-<FPGA digital electronic systems design and development examples of navigation>> source code
traffic
- Verilog HDL语言设计的交通灯设计-Verilog HDL language designed traffic light design
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
NewWayOfDPLLdesign
- 使用VHDL语言进行设计DPLL（数字锁相环）的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
xapp391_8b10b
- 8b10b design reference