资源列表
photo_verilog
- verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
FPGA_AD
- 基于Altera的FPGA开发的基于FPGA的AD转换功能，完全通过验证。-Altera s FPGA-based development of FPGA-based AD conversion function, fully validated.
yuelao
- 在QUARTUS II环境下开发的VHDL代码，实现刘德华的歌曲“月老”，本人亲自验证过。-QUARTUS II environment in the development of VHDL code, the realization of Andy Lau s song 月老 , I personally verified.
+VHDL
- 很详细用VHDL写的自动售货机程序有详细的说明和设计要求实现功能-Very detailed written using VHDL vending machine procedure is described in detail and design requirements for the realization of function
FPGAIPcAN
- 目前市面上比较流行的can协议vhdl控制器，提供源码参考设计，同仁可自行下载-At present, more popular on the market can deal VHDL controller, available in a source reference design, Tongren can download
vhdl
- 自己弄的一小段程序代码，给大家看看，望多给点意见。-Get their own small section of program code, for everyone to see, hope more points.
mini_fifo
- 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
FIFO
- 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
TranslateToUTOPIA
- VHDL写一个转换到utopia接口的转换源程序.可以进行utopia接口的仿真试验-VHDL to write a converter to convert source utopia interface. Can utopia interface simulation test
UTOPIA
- utopia接口模块VHDL源码,实现UTOPIA接口功能,可进行UTOPIA接口仿真-utopia interface module VHDL source code to achieve UTOPIA interface functions can be carried out UTOPIA Interface Simulation
project2
- 能算出CRC32 Data width 32 bit 的HDL-Is able to calculate the CRC32 Data width 32 bit of the HDL