资源列表
gaussian
- This Gaussian lvbo program please downing this matlab blur ok yes -This Gaussian lvbo program please downing this matlab blur ok yes
SDRAM_96M
- 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
UART-botelv115200
- 基于FPGA的串口收发程序，波特率115200，亲测，可用。-FPGA-based serial transceiver procedures, 115200 baud rate, pro-test, can be used.
MUX41
- 四选一的选择器 FPGA源码，包括模块Verilog文件和测试testbench文件-Four one of the selector FPGA source code, including the module Verilog files and test testbench files
ADDR
- 8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
cnt2
- 16位二进制计数器及设计代码其测试代码（vhdl）-16-bit binary counter and design codes and test code (vhdl)
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
myproject3
- 实现用FPGA控制小车循迹，和利用红外遥控控制小车-Implemented in FPGA car tracking control, and the use of infrared remote control car
Plong-master
- Pong game use VGA controller
code
- 实现RGB TTL信号的输出~可以推动任意分辨率的TFT-Achieve RGB TTL signal output- can push any resolution TFT
Filtro
- Digital filter in VHDL
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh