资源列表
01_run_led
- FPGA源码资料 采用的是EP4CE15F17C8N这个硬件平台 流水灯的源码-FPGA source code is the use of EP4CE15F17C8N hardware platform for water lamp source
02_run_flash_led
- FPGA源码资料 采用的是EP4CE15F17C8N这个硬件平台 跑马灯的源码-FPGA data EP4CE15F17C8N is used in the hardware platform of marquee source
03_key_detect_1
- FPGA源码资料 采用的是EP4CE15F17C8N这个硬件平台 按键检测的源码-FPGA source code is the use of EP4CE15F17C8N hardware platform for the detection of the source code
09_vga
- FPGA源码资料 采用的是EP4CE15F17C8N这个硬件平台 VGA的源码-FPGA source code is the use of EP4CE15F17C8N hardware platform VGA source code
about-the-experiment-of-FPGA
- FPGA相关实验程序包括点阵、A/D、D/A转换-Related experimental procedures include dot matrix FPGA, A/D, D/A converter
debounce
- 按键消抖是fpga学习 乃至编程语言学习的重要之重 我自己用的一个消抖程序真的很棒 希望对你有用 -Key jitter is an important FPGA learning and even programming language learning important to my own use of a shake out process is really great to be useful to you
VHDL
- VHDL的参考手册，具有一定的参考价值，大家可以参考学习下-VHDL reference manual, with some reference value, you can refer to learn under
delay
- PWM整流器的死区延迟的VHDL编程，可以参考一下-VHDL programming PWM Rectifier dead-band delays
32-bit-carry-look-ahead-adder
- This file contains Verilog codes
CPU_single-(2)
- 单周期CPU设计源码，基于Quatus II，亲测可用-Single-cycle CPU design source code, based on Quatus II, pro-test available
full_adder
- 用verilog语言编写的全加器模块代码，在ISE软件环境下编译开发，希望对大家有所帮助！-With verilog language full adder module code in ISE software compiler development environment, we want to help!
uart
- verilog 编写的FPGA串口报文收发程序，带奇偶校验位，并含有DS18B20温度传感器驱动程序，可以自行设置波特率.-verilog prepared by the FPGA serial transceiver procedures packets with parity, and contains a temperature sensor DS18B20 driver, you can set the baud rate yourself.