资源列表
Stepper-motor
- 步进电机驱动模块设计，使用硬件描述语言设计。-Stepper motor driver module design, using a hardware descr iption language design.
Stepper-motor-speed
- 步进电机控制模块主要包括步进电机调速控制，该模块实现步进电机可由外置拨码开关来控制电机转速。-Stepper motor control module comprises a stepper motor speed control, the stepper motor module by external DIP switches to control the motor spe
BERT.ZIP
- BER test for asynchronous interface, e.g.RS485, RS232. selectable 2^11 or 2^15.
Descending-ramp
- 递减斜波是一种原理和递增斜波相似的波形，只需将递增斜波的循环加法计数换成1111 1111 1111～0000 0000 0000循环减法计数即可。-Harmonic is a descending ramp and incremental principle similar waveforms, simply incremented counts up the ramp into the cycle of ~ 1111 1111 1111 0000 0000 0000 cycle counti
VHDL_paobiao
- 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
DE2_Basic_Computer
- DE2 altera board vhdl design
vhdl416yima.doc
- 四十六译码器 是用if语句描述的-library IEEE use IEEE.std_logic_1164.all entity encoder4_16 is port ( d: in STD_LOGIC_VECTOR (3downto0) q: out STD_LOGIC_VECTOR (15downto0)) end encoder4_16 architecture encoder_if of encoder4_16 is begin
QAM
- QAM基带调试，星座映射方法，带有m序列作为信源-QAM baseband debugging, constellation mapping method
m
- 为随机序列产生器，可以作为调制信号的信源-As the random sequence generator, can be used as a modulation signal source
IQ_sin_cos
- Cordic根据输入的IQ正交两路信号求取对应的正余弦值-Cordic according to input the IQ of orthogonal cosine signal to calculate the corresponding two road is
IQ_sin_cos_mod
- Cordic根据输入的IQ正交两路信号求取对应的正切值-Cordic according to input the IQ of orthogonal signal to calculate the corresponding tangent value two road
my_i2c
- 基于FPGA的i2c通信，使用Verilog hdl实现，带有功能说明文档、ise工程、modelsim仿真工程-i2c communication based FPGA using Verilog hdl implementation, with the function documentation, ise project, modelsim simulation project