资源列表
RFID_VERILOG_1988
- RFID Reader using verilog
UART_DPLL
- 通过串口uart rs232控制的全数字锁相环，dpll， 可锁时钟相位-UART CTORLER DPLL MODULE CLK
code_clk_nco
- 码时钟发生器，可灵活配置参数，根据比例得到自己所需的码时钟，可用于扩频通信-CODE CLK MODULE CDMA
max485
- 自己写的RS485的通讯程序，调试通过的，可以作为初学者的入门程序。-Write your own RS485 communication program, through debugging, as a beginner entry procedures.
Adder4bit
- VHDL full adder 4 bit
Adder4bit7Segment
- vhdl adder 4 bit to 7segmnet
7Segment
- vhdl seven segment code
BCDto7Segment
- vhdl bcd to seven segment
7Segment2bcd
- vhdl seven segment to bcd 4 bit
7Segment2bcd8bit
- vhdl seve segment to bcd 8 bit
freq_meter
- FPGA的测频程序，用了D触发器，能测1hz到几百hz-FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz
jiaotongdeng
- 基于FPDA的交通灯课设，功能老师以及验证过，真实能用。各模块截图也有，方便理解-FPGA-based class-based traffic light, functional and verified teacher, real use. Each module also has a theme, easy to understand