资源列表
vivado_2014-4_2015-2_64bit
- vivado 2014.4-2015.2 64bit的全部license-vivado 2014.4-2015.2 64bit license
timer
- 数字秒表，按键+数码管 上电后数码管开始计时，精度1/10秒： 按 SW2 ：复位（清零后重新计数） 按 SW3 ：暂停 按 SW4 ：继续计数-Digital stopwatch, key+ digital tube after power digital control start timing, precision 1/10 sec: Press SW2: Reset (after a re-count is cleared) by SW3: Pause Press SW4
LCD1602
- 由于 1602 是慢速设备，根据我们显示网址 32 个字符的架构，我们在顶层设计了一个FIFO, 在开始工作的时候一次性把要显示的字符传到在LCD1602上显示RedCore网址 FIFO中，在1602控制层代码中再从FIFO读出送 去显示，加FIFO的好处是，高速的TOP层可以不用去等待慢速的1602写时序，把两个层次的模块 独立开来。-Since 1602 is a slow device, according to our display URL to 32 charac
ALU
- This code contains three architech for only entity
Component_instanlations
- This an example for component_instanlations in VHDL languege-This is an example for component_instanlations in VHDL languege
Multiplexer
- This a example for Multiplexer. It is wrote in ISE xillin -This is a example for Multiplexer. It is wrote in ISE xillin
BCDTo7SEG
- This is a example for BCD to 7SEG. This code is wrote in VHDL
Bell2
- This an example for control a Bell in VHDL languge-This is an example for control a Bell in VHDL languge
AD7612V3
- Verilog Code of AD7612
N_CSMA
- 一种CSMA原理的描述性仿真编程，实现了站点间的类CSMA通信-One kind of CSMA descr iption of the principle of simulation programming class that implements the CSMA communication between stations
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
EDA-digital-clock
- 显示时、分、秒，有手动校时功能，计时过程具有报时功能-Display hours, minutes, seconds, manual timing function, timing processes with chime