资源列表
VHDL测频率周期
- 用VHDL语言编写的频率计程序，用来测量方波的频率以及周期。
7-16
- CIC滤波器的VERILOG HDL语言实现，通过QUARTUSII软件编译通过，仿真结果是正确的
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
PPPdecoder
- decoder in vhdl A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders because they are simpler to design.
fadder4
- 例化语句生成的四位全加器代码，写在word里了，也有MODELSIM测试代码-Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code
spartan3E-seg-driver
- spartan3E seg display driver-spartan 32 seg display driver
paomadeng
- 这是一个跑马灯项目，语言为verilog，basys3开发版开发。-this is a project about paomadeng.
eeprom_test
- eeprom的读写程序 veriloghdl实现 基于xilinxsparten6-eeprom literacy program veriloghdl Based xilinxsparten6
31_Greedy_snake
- 贪吃蛇小游戏 verilogHDL语言描述 基于xilinxsparten6板子 -Snake game verilogHDL descr iption language based xilinxsparten6 board
8 bit, bit by bit procesing unit
- This module does an bit by bit sum, 2 complement,or,and,xor,and not operation of two 8 bit numbers (not and 2 compliment its just 1 number) It has two shift registers that feed your numbers to the procesing unit with an external load/shift signal and
Maxplus2_74LS161
- 用Maxplus2制作的实现74LS161数字芯片功能，入门级工程。-Maxplus2 made with digital chips to achieve 74LS161 function, entry-level engineering.
RGMII
- 用xilinx芯片实现千兆网的实例代码，您可以通过修改此代码完成基于ETMAC IP核的MAC设计，驱动外部PHY芯片或进行MAC to MAC 的直连通信设计。-this is code of etmac IP inst.. it will help you developing for MAC and PHY