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  1. VHDLtlight

    0下载:
  2. 智能控制交通灯。分主路辅路,当辅路无车时主路保持绿灯,当辅路有车通过时辅路亮绿灯,并且在最短五秒钟之后或者20秒之内返回原来的状态。-Intelligent control of traffic lights. At the main road and side roads, as roads without the green light when the main road to maintain, when the roads when the roads a car through a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:2.76kb
    • 提供者:小白
  1. firewire

    0下载:
  2. IP CORE .VERY GOOD AS A STUDY FILE-IP CORE. VERY GOOD AS A STUDY FILE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:103.15kb
    • 提供者:lijun
  1. FFTProcessor

    0下载:
  2. IP CORE .VERY GOOD AS A STUDY FILE-IP CORE. VERY GOOD AS A STUDY FILE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-04
    • 文件大小:1.01mb
    • 提供者:lijun
  1. Keyboardcontroller

    0下载:
  2. keyboardcontroller IP CORE .VERY GOOD AS A STUDY FILE-keyboardcontroller IP CORE. VERY GOOD AS A STUDY FILE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:7.14kb
    • 提供者:lijun
  1. Embedded_risc

    0下载:
  2. Embedded_risc IP CORE .VERY GOOD AS A STUDY FILE-Embedded_risc IP CORE. VERY GOOD AS A STUDY FILE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:124.43kb
    • 提供者:lijun
  1. AVR_Core

    0下载:
  2. AVR_Core IP CORE .VERY GOOD AS A STUDY FILE-AVR_Core IP CORE. VERY GOOD AS A STUDY FILE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:68.38kb
    • 提供者:lijun
  1. Bluetooth

    0下载:
  2. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:12.77kb
    • 提供者:lijun
  1. l2woM1Nz

    0下载:
  2. 一些比较实用的例子,希望能给大家带来帮助。-Some more practical examples, we hope that they will be helpful.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-25
    • 文件大小:492.91kb
    • 提供者:晓贞
  1. StateMachine

    0下载:
  2. 典型的状态机,简单的状态机可以不需要编码,也可以采用one-hot编码方式,如果状态很多时,采用格雷码,能有效避免亚稳态。-A typical state machine, a simple state machine can do without coding, can also be used one-hot encoding, if the state in many cases, the use of Gray code, can effectively avoid metastable
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:1.06kb
    • 提供者:吴长瑞
  1. srbjq

    0下载:
  2. vhdl实现的三人表决器,大家一起交流一下,-VHDL realization of three voting machines and we can work together to exchange about
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:1.11kb
    • 提供者:孟旭
  1. internet_FPGA

    0下载:
  2. 介绍了Xilinx最新的EDK9.1i和ISE9.1i等工具的设计使用流程-Xilinx introduced the latest EDK9.1i and ISE9.1i the use of tools such as the design process
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:140.09kb
    • 提供者:伍迪
  1. VHDL

    0下载:
  2. 电子抢答器VHDL语言设计 材料是一图文格式的可能需要读者自己打上去 不过绝对真实-Answer electronic device materials VHDL language design is a graphic format, the reader may need to play up its own absolutely true, however
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.73mb
    • 提供者:陈明
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