资源列表
121111
- 关于FPGA和单片机的PCB板的开发原理图，以及相关的单片机程序设计-On the FPGA and PCB MCU development board schematics, as well as related Singlechip Programming
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
shifter
- 完成一个加速器设计，全加器，具 8位计数器-Complete a accelerator design, full adder, an 8-bit counter
modelsim
- modelsim 使用教程,verilog或vhdl仿真-ModelSim use tutorial, verilog or VHDL simulation
VerilogHDL
- 这是一本pdf格式的电子书，书名是VerilogHDL，将一种硬件描述语言-This is a pdf format e-books, the title is VerilogHDL, will be a hardware descr iption language
lock
- 电子密码锁，实现并行输入，错误报警和密码设置功能，以及兼作门铃使用-Electronic code locks, the realization of parallel importation, error alarm function and password settings, as well as the use of doubles as a doorbell
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
ASIC_and_FPGA_Verification
- ASIC/FPGA验证经典资料，英文版，希望大家可以有所借鉴。-ASIC/FPGA verification classic information, in English, I hope that we can learn from there.
FPGA_PCB
- 高速FPGA的PCB设计指导.WORD文档格式-High-speed FPGA-PCB design guidelines. WORD document format
SCHK
- 实验图1是一含计数使能、异步复位和计数值并行预置功能4位加法计数器，例1是其VHDL描述。由实验图1所示，图中间是4位锁存器；rst是异步清信号，高电平有效；clk是锁存信号；-Figure 1 is a test with count enable, asynchronous reset and preset features include numerical parallel adder four counters, Example 1 is described in VHDL. By e
mux21a
- 在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。-VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in para
mux21a
- 2选1多路选择器的VHDL完整描述，即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete descr iption of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is th