资源列表
zj
- vhdl编程的，移位寄存器，八位，支持左移，右移-VHDL programming, shift register, 8, support the left, shifted to right
VHDL
- 状态机及其VHDL设计,详细介绍了状态机的基本结构、功能和分类，以及有限状态机的一般设计思路与方法、状态机编码方案的恰当选取、Moore和Mealy状态机的本质区别及设计实现-State machine and the VHDL design, described in detail the basic structure of state machines, function and classification, as well as finite state machine of the
20084142011081129
- VHDL设计举例：直流电机控制器.docgfddrhd-VHDL design, for example: DC motor controller. Docgfddrhd
dbg_interface
- USB v1.1 RTL and design specification
binary_to_gray
- 将二进制数转化为格备码，4位并行。binary_input为二进制数输入， gray_output为格雷码输出。-Will be converted into binary code grid preparation, 4-bit parallel. binary_input for binary input, gray_output for the Gray code output.
cntm60
- 这是六十进制计数器的源程序，有需要的同学可以参照一下！-This is a six decimal counter source, needy students can refer to you!
cnt24_t
- 这是二十四进制计数器的源程序，有需要的同学可以参照一下！-This is 24 hexadecimal counter source, needy students can refer to you!
CNT10_T
- 这是同步十进制计数器的源程序，有需要的同学可以参照一下！-This is a source synchronous decimal counter, needy students can refer to you!
CNT10_P
- 这是消除毛刺十进制计数器的源程序，有需要的同学可以参照一下！-This is counter to eliminate glitches decimal source, needy students can refer to you!
F_adder
- 这个源程序是关于全加器的，又需要的同学可以借鉴一下 -This source code is on the full adder, and also the needs of students can learn from you
gen_tb
- 用于verlilog自动产生testbench的脚本 用法：gen_tb <yourfilename>-Testbench for verlilog automatically generated scr ipt usage: gen_tb <yourfilename>
Execise
- altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation