资源列表
verilogAlwaysblockexplanation
- verilog下always模块的介绍，以及怎么用always模块实现组合逻辑和时序逻辑，阻塞和非阻塞的深入介绍。-verilog：always block introduction
key_add
- FPGA实现移位加法器，验证可靠，用于实验课和平日科研，方便移植-FPGA Implementation shift adders, verification and reliable, and weekday classes for scientific experiments, to facilitate migration
ad9288
- 使用FPGA控制AD9288，方便移植，可以拿来直接使用，适合新手学习-Use FPGA control AD9288, easy migration, can be used to directly use for novices to learn
dds
- 使用FPGA产生DDS信号发生器，方便移植，适合新手学习，开发环境Q2-Use FPGA generate DDS signal generator, easy migration, suitable for novices to learn, develop environment Q2
moore
- FPGA实现moore状态机，适合新手学习，开发环境Q2-FPGA implementation moore state machine, suitable for novice learning, development environment Q2
sram
- FPGA控制SRAM读写时序源码，代码桂发，新手一看就懂-FPGA control SRAM write timing source code Guifa novice understand at a glance
SegLed_DynamDisp
- 用FPGA是休闲其工作原理，结果为SEGLED动态显示-FPGA is casual with their works, the result is displayed as SEGLED dynamic
i2c
- wishbone to avalon 介面 I2C-wishbone to avalon I2C interface
Exp1_Part234
- Altera Exp1_Part2,3,4 for DE0
Exp1_Part1
- Altera Exp1_Part1,2,3 for DE0
inc_pid
- 基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set-Incremental PID FPGA-based design methodology
cl_rx
- cameralink总线接口代码，用于接收cameralink协议传输的图像数据。从芯片随路时钟域切换到系统时钟域。 做cameralink接口相关的图像采集系统可以参考。其中的ram是lattice工具生产的。-cameralink bus interface code for the image data receiving cameralink protocol transmission. Switching chip clock domains with the way the sys