资源列表
SystemVerilog-for-Verification
- 经典的system verilog 教程。英文原版。-system verilog english version ， very useful
IPRAM
- FPGA内置RAM,调用tools里面的IP核，生成一个双口的RAM，用来存储数据。然后可以用SignalTAP II查看波形或者数据。-FPGA built-in RAM, which is called IP core tools to generate a dual port RAM, used to store data. You can then view the waveform or use SignalTAP II data.
VHDL_codes
- include VHDL code -include VHDL code
8086vga
- ：两人乒乓球赛 Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard
FPGA-DDS-algorithm
- 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
jtd
- 交通控制灯的设计源码和仿真波形，和逻辑单元结构图-The design of traffic control light source and simulation waveforms, and the structure of logic cells
FPGA
- FPGA development vhdl
DA_TLC5615s-Voltage-on-Digital-tube
- 使用10位串行DA芯片TLC5615将数字信号转换为模拟信号，开发板DA芯片VDD=5V,VREF=3.3V 计算公式：Vout=VREF*(N/1024) N为10位二进制码 最后使用开发板上AD芯片TLC549将电压显示于数码管上-use 10 serial DA TLC5615 and display on digital tube
add_success
- 在ise中，实现两个ip核分别做加数和被加数，并将结果存在另一个ip-In ise, the realization of two summand and ip nuclear summand were done, and the results there is another ip
quartusandniosshiyong
- quartus与nios的联合使用，简单示例-quartus and nios use of a simple example
System-Verilog-for-Verification
- System Verilog for Verification，第二版，Chris Spear著的，对System Verilog的仿真与验证描述的很详细-System Verilog for Verification，Second Edition
DDS
- 这是一个任意频率的正弦信号发生器，具有可改变输出信号频率，输出信号相位，任意转换输出信号类型（正弦、余弦、锯齿波、方波），屏幕可分别显示用户设定的信号频率与输出信号检测频率。-This is an arbitrary frequency sinusoidal signal generator, with can change the output signal frequency, the output signal phase, arbitrary conversion output sign