资源列表
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
electronic-clock
- Verliog HDL数字系统设计项目，电子钟。该电子钟可以实现时钟、日期、闹钟、秒表功能。-Verliog HDL digital system design projects, electronic clock. The clock can clock, date, alarm clock, stopwatch function.
DDR
- 关于DDR布线规范，用于指导PCB布线.-Wiring on the DDR specification, PCB layout for
ROM
- vhdl中的ROM程序，包括matlab表格程序，调用FPGA里的RAM实现ROM功能-The ROM vhdl procedures, including matlab spreadsheet program, call the FPGA to achieve ROM functions in the RAM
test8
- 这是一个Verilog编写的VGA驱动程序，该程序在FPGA开发板上运行后，能在VGA显示上显示一个行走人的动画-This is a VGA driver in Verilog, the program running in the FPGA development board can display a person s walking animation on a VGA display。
Ma-baker7
- This corde generate Baker signal user DDS ipcore
Baker code
- This is a project to create a baker code, used in radar signal processing.
lab1
- 电子琴，自动播放，手动播放，录音功能-Keyboard, autoplay, manual playback, recording function, etc.
ICT
- 96x96 Digital MUX/DEMUX via SPI
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
hill
- 本文介绍基于NiosII系统的家庭健康专家的设计。该设备定位于医疗保健领域内的家用电子产品，为家庭各个成员提供健康测量、健康教育、科学锻炼与数据综合等功能。设备采用了uC/OSII实时操作系统，可灵活的自定义外设，实现了大容量的数据存储，友好的用户界面和可靠的系统控制。-This article describes the design based on NiosII system of family health experts. The positioning of the device i
nios
- quartus nois教程 使用并行FLSH作为存储 有效的完成nois相关设计-quartus nois tutorial uses the effective completion of the nois related design FLSH as the storage in parallel