资源列表
Dchufaqi
- VHDL实现D触发器包括上升沿触发，下降沿触发，时钟触发-VHDL realize D flip-flop including rising along the trigger, falling edge trigger, triggered the clock
Lab2
- Flip-flops with enable
LCD
- 基于FPGA和Nios II的12864LCD驱动代码-Based on FPGA and Nios II of 12864LCD driver code
liushuideng
- 使用ise写的并行流水灯，体验顺序执行和并行的概念，容易学习-Use ise write parallel water lights, concept experience sequential and parallel execution, and easy to learn
CCD_Sim
- 用verilog HDL语言编写的面阵CCD相机输出图像程序。-The CCD camera output image process using Verilog HDL language.
paral_to_serial
- 用verilog HDL编写的并行接口转串行接口的程序。-The programming of parallel interface to serial interface with HDL verilog.
fenpin
- 用verilog HDL编写的任意数分频，包括偶数分频和奇数分频等。-The any number of points, including even frequency and odd frequency, etc..using Verilog HDL
mux3x2
- 基于VHDL的3选2功能元件的Quartus II实现-Based on 2 out of 3 functional elements Quartus VHDL realization of II
dengjingdu
- 数字频率计，2015国赛题目，可实现所有功能，整形电路无问题的话，测量结果几乎无误差！-Digital frequency meter, the 2015 National Games, can achieve all the functions, no problem of the plastic circuit, the measurement results are almost no error!
key_scan
- 这是一个FPGA的按键扫描程序，无需延时就可以实现软件消抖，是一种创新的消抖新方法！-This is a FPGA key scan program, without delay can achieve software to shake, is a new method for the elimination of innovation!
FIFO
- First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。-The abbreviation of the first input first output, the first in first out queue, which is a traditional sequential execution method, first enter the command to finish and retire
fir_lms
- 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA