资源列表
gold_code_generator_rank10_b
- 通信扩频码GOLD码序列的产生，码长度可以手动设置，VHDL语音实现。-GOLD generate communication code sequence spreading code, the code length can be set manually, VHDL voice implementation.
dds_clk
- VHDL代码实现FPGA中DDS功能，输出频率可调-VHDL code for the FPGA DDS function, the output frequency is adjustable
自定义PWM IP核，符合avalon总线
- 适合初学qsys、nios者，含tb文件，仿真通过，无bug
AD_SAMPLE_PHASE_MATLAB
- 测试多通道AD同步采集信号的相位差,经过实际项目验证-test multi-channel AD sample signal s phase
modelsim-C_compiler_issue
- modelsim的C compiler问题，请需要者下载参考-modelsim the C compiler problem, for those who need to download reference
sample-vhdl
- basic vhdl codes for beginers
I2Creadorwrite
- 基于MAX II 系列 epm1270t iic的读写-Based on the MAX II family literacy epm1270t iic
siga
- 2014电子设计大赛e题固件模块代码，很好的实现功能。-2014 electronic design contest e Title firmware module code, very good to achieve function.
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
New-Compressed-(zipped)-Folder-(4)
- verilog code for sequence detection implemented on FPGA using quartus simulator
New-Compressed-(zipped)-Folder-(5)
- traffic light controller verilog code modelsim tested
meexternalletterforcsvtu
- ! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access the file because it is being used by another process. -! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access