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  1. IP核的生成

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  2. 讲述了FPGA中IP核的使用方法,对于初学者很有帮助。(The method of using IP core in FPGA is described.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:3079168
    • 提供者:jihan
  1. SPI_controller

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  2. SPI controller (fpga/verilog)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:119808
    • 提供者:taso999
  1. 基于IP核的ISE设计流程

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  2. 讲述了在ISE中如何通过建立ip核,使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:2491392
    • 提供者:jihan
  1. spi master slave

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  2. SPI master slave (fpga/verilog)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:67584
    • 提供者:taso999
  1. Coding Files

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  2. Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:12288
    • 提供者:kutti
  1. Coding files

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  2. The past several years have witnessed a rapid development in the wireless network area. So far wireless networking has been focused on high speed and long range applications. Zigbee technology was developed for a Wireless Personal Area Networks WPAN
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:8192
    • 提供者:kutti
  1. Coding Files

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  2. We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:27648
    • 提供者:kutti
  1. Coding Files

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  2. Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:52224
    • 提供者:kutti
  1. wangfei

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  2. 基于FPGA的一个LCD显示的网费计价系统设计(costing system of network)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:3072
    • 提供者:月月1234
  1. slave_control

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  2. VHDL实现spi,从机实现方法,实现32个bit传输,单向传输。(VHDL implementation of SPI, from the machine implementation method, the realization of 32 bit transmission, one-way transmission.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:1024
    • 提供者:许大牛
  1. Verilog_1Gb_DDR3_G_Die

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  2. ddr3控制器,速率可达1Gbps,语言使用verilog,已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:33792
    • 提供者:aikannba
  1. VHDL程序

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  2. 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真,并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
  3. 所属分类:VHDL/FPGA/Verilog

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