资源列表
part5_update
- 2个4位二进制数相加的加法器件，其结果显示在七段译码器中-two four binary adder Addition of a few devices, and the results showed that in paragraph 107 of the decoder which
DS18B20+VHDL
- 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
NAND256R3A_VE1
- 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
fulleradder
- 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim
decoder24
- 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了一个简单的译码器，适合处学者-the procedures to XILINX ISE8.2 for the development platform VHDL language for the development and achieve a simple decoder, the Department for scholars
ClockDiv
- 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
DELAY1
- 本程序以ISE为开发平台，采用VHDL为开发语言，实现了对一个时钟信号延时的功能-the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
CCDOUT
- CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言，以ISE为开发平台，产生了模拟CCD信号的数字信号，只需经DA转换便能实现-CCD signal because of its uniqueness, not generally produce a signal source, the procedures used VHDL, ISE as a development platform, have CCD signal simulation of digital signa
i2cjiekouchengxu
- 这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
DDS_VHDL_xzy
- 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器，芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
freq8
- 在EDA软件上编程，利用VHDL语言编程实现8位频率计-in EDA software programming, the use of VHDL programming eight Cymometer