资源列表
i2cjiekouchengxu
- 这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
DDS_VHDL_xzy
- 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器，芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
freq8
- 在EDA软件上编程，利用VHDL语言编程实现8位频率计-in EDA software programming, the use of VHDL programming eight Cymometer
VHDLEXAM
- 我们学校做VHDL实验的源码，在别处是下不到的-our school experiment VHDL source code, elsewhere is less than the
memoryuse
- Verilog HDL语言在FPGA实现中的存储器的使用详细说明-Verilog HDL language in the FPGA memory of the use of detailed
vhdl_sw_lr
- 我自己写的vhdl程序，内有画图器，ram 和控制ram。还有test bentch。-I wrote it myself vhdl procedures, which are drawing device, and control of ram ram. There bentch test.
VCDwtHDLV
- < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘
03034
- verilog中的一个不用状态机和决断函数就可以实现多重函数赋值的例子，希望对你用帮助。-verilog of a state machine and no decisive function could achieve multiple functions assigned to the case, you want to help.
modelsim_guide_cn
- modelsim操作指导 很适合入门 有实例-modelsim operation guidance is very suitable example of a portal
sourceIIR6
- IIR 六阶数字滤波器的 VHD L 描述-six-IIR Digital Filter Volume L Descr iption
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
liangzhu
- 基于max—plus2开发环境，设计的《梁祝》演奏曲-based max-plus2 development environment, the design of the "Butterfly Lovers" concert song