资源列表
and_2
- 自己设计的一个简单的与门设计。新手初学，请多多指教。-own design with a simple design of the door. Novice beginner, please exhibitions.
b8bit_adder
- 8位的加法器设计，分4个工程完成的，用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
redandyellow
- 交通灯，十字路口红绿灯的VHDL程序，绝对可用-traffic lights, traffic lights crossroads VHDL procedures, absolutely available
Quartus_vhdl
- 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
VHDLchufaqi
- MAXPLUS2 自己编写的VHDL 4位除法器-MAXPLUS2 prepare themselves VHDL four Divider
index
- 实现二进制长串的算术右移的操作。希望有点参考价值。可以直接运行，多提意见咯。。。谢谢`-achieve long strings of binary arithmetic right side of the operation. Want a little reference value. Direct operations and opinions 1,10. . . Thank you, `
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori
cordic_1-0
- Cordic算法的另一种C++实现，只是一个样本，可以用TubroC，等来查看-Cordic algorithms to achieve another C is a sample that can be used TubroC, etc. to see
RAM_VHDL_34
- RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL descr iption RAM's VHDL descr iption RAM's VH DL described in VHDL's RAM
chipscope_vhdl_fpga_xilinx
- chipscope使用教程 以及 FPGA 在线调试的方法-chipscope directory and on-line debugging of FPGA methodology aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa
taxi_counter
- 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation,
licheng
- 本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.-Verilog the procedures for scanning into the keyboard, then were sent to 51 micro-processing procedures.