资源列表
pingche
- 简易数字频率计，数码管显示，VHDL语言-simple digital frequency meter, digital control, VHDL
qiangdaqi4ren7.1
- 四人抢答器的实现，主持人按键清除按键，按开始键，100秒倒计时答题时间-four Responder the realization host keys to remove the keys, according to begin key 100 seconds to answer in the countdown time
dianzheng6.2banben
- 8*8点阵的实现，循环显示vhdl四个字母-8 * 8 lattice the realization cycle shows vhdl four letters
dig_clk_lcd
- 数字钟的实现，由LCD动态显示，VHDL语言实现-the realization by the dynamic display LCD, VHDL
ps2_lcd_1602
- 与PS2的通信，PS2按键值发给LCD显示，VHDL语言。-communication with the PS2, PS2 keys to the value of LCD Display, VHDL.
chuanbingzhuanhuan
- VHDL代码，仿真通过，变异可以，下载变成文件，但需要修改，串并转换-VHDL code, through simulation, the variation can be downloaded into a document, but need to change, and change series
1_061026140305
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language. - Based on the FPGA I2C main line simulation, verilog uses the HDL la
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
vhdl_led
- 7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7，-seven of the digital control experiments (including two experimental), the digital control of a Test : Dynamic scanning approach to the eight digital control "at the same time" show 0 -7
1_070116141639
- verilog编程ps2接口设计,基于fpga的设计-verilog ps2 Programming Interface design, the design based fpga
vhdl_buzzer
- 蜂鸣器实验 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状 态机和分频器使蜂鸣器发出“多来咪发梭拉西多”的音调。-buzzer to buzzer this experiment certain frequency square wave can buzzer sounded a corresponding pitch. The experiment by designing a state machine and the buzzer sounded a d
vhdl_dial
- 拨码开关实验 拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。-dial-switch dial-switching experiment 8 0 1 state in seven of the eight corresponding digital control-show or a 0.