资源列表
vhdl_i2c
- 7． IIC 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址，按动另 外一个键，将刚写入的数据读回CPLD，并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。-7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data sw
vhdl_traffic
- 模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程，用LED 灯表示交通灯，并在数码管上显示当 前状态剩余时间。-simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display th
vhdl_clock
- VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends
sampleVHDL
- 采样等精度测量的VHDL程序．．在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
bujindianjiVHDL
- 步进电机定位控制系统VHDL程序与仿真波形．已经在xilinx ISE 8.1上验证．完全正确．-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
Uart2
- uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
vhdlvga
- Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 语言写的在显示器上显示图案的程序-writes with VHDL Language demonstrates th e design on the monitor program with the source VHDL The language was on display in the pictorial proc
pcm(8)
- 语音编码的VHDL源码,已经调试通过.压缩文件中包括调试过程代码.-speech coding VHDL source code, debugging has been adopted. Compressed files to include debugging code.
pskask
- 用C语言，实现PSK与ASK的二进制调制-C language, and the realization of PSK modulation binary ASK
juanji2
- 用TI DSP汇编指令进行程序设计：“TIC54XDSP汇编程序设计-卷积-compiled using TI DSP Programming instructions : "TIC54XDSP compilation of program design-convolution
autofir
- 自适应滤波器设计的仿真程序，完全用C语言编写，可以作为滤波器设计的参考。原为VHDL实验要求的程序。-adaptive filter design simulation program, complete with C language can be used as filter design reference. VHDL to the original requirements of the experimental procedures.
MIT_MIPS_Core.tar
- 麻省理工的一个实验室实现的MIPS IP CORE，可以在FPGA上跑通 -a Massachusetts Institute of Technology laboratory achieved MIPS IP CORE, the FPGA can run on Link