资源列表
fpgacaiji
- 自己课程设计写的程序，用FPGA控制ADC0809的转换时序来完成模/数转换，然后将转换完的数字信号传递给0832-write their own curriculum design process, Connection between ADC 0809 FPGA control the timing to complete the conversion analog / digital conversion, End then converting the digital signal to
20040810319xiyijiVHDL
- 自己 写的课程设计 ，用vhdl写的模拟洗衣机，希望对大家有帮助-himself wrote the curriculum design, simulation vhdl wrote washing machines, we hope to help
CHENGFAQI
- 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary -
verilog111
- verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦-verilog things properly used it, it is an essential learners verilog things oh
DJDPLJ_T
- 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1 -- 100M
ddschengxu
- dds程序 有原理图 代码 哈哈 dds程序 有原理图 代码 -dds procedures diagram code says dds procedures diagram code
mipsinverilogandvhdl
- mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
vhdlfinishcpu
- 用vhdl实现简单cpu的功能,能够很好的帮助特别是初学者学习vhdl的功能!-with vhdl cpu to achieve simple function can be very helpful, especially beginners learning vhdl function!
vhdlduogelizi
- 多个VHDL程序,跟大家参考,交流,谢谢,了,大家 -many VHDL procedures, with reference exchange, thank you, and we
crc_32_16
- crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Bintograyconverter
- 二进制到格雷码转换ASD ASD ASD-binary Gray code conversion to ASD ASD ASD ASD ASD
mimasuo2S50
- 8位密码锁的实现，初始状态默认为密码正确，密码输入正确方可设密码，以后必须按对密码才可重设-8 password lock the realization of initial state defaults to the correct password, the password can input the correct password. After the password must be re-established before