资源列表
gtx_interface_ip
- 高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
apb_slave_latest.tar
- APB slave master uding verilog
ug480_7Series_XADC
- xinlinx V7芯片 用verliog 和vhdl 实现自带adc的模拟量采集-xinlinx V7 chip with verliog and vhdl realization comes adc analog acquisition
top_clock-plus
- 在quartus ii上仿真24小时的时钟在输入基本的时钟信号后，秒数，分数，小时数的变化-After entering the basic clock signal, seconds, fractions, changes in the number of hours of simulation on a 24-hour clock quartus ii
ARINC_429
- FPGA实现ARINC429协议，利用verilog HDL做了完整的ARINC429通信收发协议，EDA开发平台为quartus ii9.1。-FPGA implementation ARINC429 protocol using verilog HDL to do a complete ARINC429 communication transceiver protocol, EDA development platform quartus ii9.1.
14_ethernet_test
- 这是利用FPGA实现对以太网传输的控制。FPGA为Spartan 6 LX16，以太网芯片为RTL8211。千兆传输速率。语言为Verilog，但没找到这一选项，故选择了最接近的VHDL-This is achieved using the FPGA Ethernet transmission control. FPGA for the Spartan 6 LX16, Ethernet chip RTL8211. Gigabit transmission rate.
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
OExp11-OwnMCPU
- 浙江大学计算机组成实验课工程代码，多周期CPU设计控制器实现。-Multi-cycle CPU design of the controller.
hdmi_demo
- hdmi 视频编解码输入输出模块，verilog实现-hdmi encoder and decoder in verilog.
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
fsmc_fpga
- FPGA和STM32通讯的例子，keil和quartus软件程序-Examples of FPGA and STM32 communications, keil and quartus software program
svpwm
- SVPWM verilog source code