资源列表
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
zhangnan11
- 一个基于FPGA的洗衣机正反转定时控制器，可以在开发板上实现控制和显示功能(A FPGA based washing machine is reverse timing controller, you can control and display functions on the development board)
121114156PCIE_DMA_DDR3_verilog_design
- 基于FPGA的pcie dma设计，可参考应用。(FPGA based PCIe DMA design, you can refer to the application.)
jesd204
- xilinx平台 jesd204核例化使用示例(Xilinx platform jesd204 core example of the use demo)
LatticeECP3_SERDES_PCS_使用指南
- LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)
UART
- 自己总结的UART的设计及分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
traffic_light
- 设计一个简单的交通灯控制器，交通灯显示用实验箱的交通灯模块来显示。系统时钟选择时钟模块的1Hz时钟，黄灯闪烁时钟要求为1Hz，红灯15s，黄灯5s，绿灯15s。系统中用CPU板上的复位按键进行复位。(Design a simple traffic light controller, traffic lights show the use of the experimental box traffic lights module to display. System clock select cl
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
HanoiTower
- 使用Verilog HDL 以及VHDL语言，运用FPGA中的VGA显示原理以及键盘控制原理，开发汉诺塔简易游戏(The use of Verilog HDL and VHDL language, the use of FPGA in the VGA display principle and keyboard control principle, the development of Hanoi simple game)
digital_clock
- vivado 学习资料 数字时钟设计 新建工程后导入相关文件（source）(digital clock Vivado learning materials Digital clock design, new construction, import related documents (source))
AD9777
- 基于FPGA平台设计的AD9777芯片的代码(AD9777 chip design based on FPGA platform code)
夏宇闻Verilog经典教程
- 夏宇闻经典教程，里边有几个章节讲的比较好，初学者可以参考(Xia Yuwen classic tutorial, there are a few chapters about the better, beginners can refer to)