资源列表
FPGA-CPLD_DesignTool(5-6)
- FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
FPGA-CPLD_DesignTool(example3-4)
- FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载-FPGA-CPLD_DesignTool. 3 -4 examples procedures have requested upload download a friend in need
VHDL-jishushizhong
- 这是一个用VHDL编的一个计数时钟的设计,程序各个模块都有,希望和大家多多交流-This is an addendum to the VHDL a clock counting the design, each module has procedures, and we hope to conduct more exchanges
MAXplusqiangda
- MAXplus抢答器课程设计做了很久的验证通过-MAXplus Responder course design a long time ago passed the test
simple_clock_VHDL
- (1)具有时、分、秒计数显示功能，小时为24进制，分钟和秒为60进制。 （2）可以根据需要设置复位、清零、置位等功能。 -(1) with time, minutes and seconds count display, 229 hours for 24, 50 minutes and 60 seconds for the 229. (2) can be reset according to the need, resetting, home spaces, and other fu
pcm13
- ＰＣＭ采编器器系统是一种常用的遥测设备，它可以采集多路数据并进行通信传输和数据处理，PCM 采编器控制采集各个数据通道数据的时序，并加上帧同步码形成一定格式的数据，再进行并/串转换，形成串行数据流送到调制设备供传送。-PCM Editor System is a common telemetry equipment, It can be multi-channel data acquisition and communication transmission and data processin
2FSK2psk
- ２ＦＳＫ２ＰＳＫ－二进制频移键控和相移键控信号发生器的源程序，是基于ＱＵＡＲＴＵＳ ＩＩ软件平台，使用ＶＨＤＬ语言-2FSK2PSK-binary frequency shift keying and phase shift keying signal generator source, QUARTUS II is based on the software platform, the use of VHDL
vhdladc0809
- adcint,是adc0809的采样控制器设计!-adcint is adc0809 sampling controller design!
1231314141
- 是用VHDL编写的电子时钟，用两个键控制，在选中调节时，该位还闪烁。-VHDL is prepared by the electronic clock with two key control, the selected adjustment, the place still blinking.
exp03_PCI
- PCI设备查询及其配置空间的读取,Win9X/me下可以用,显示数据含义可查看PCI22规范中的介绍-inquiries and equipment PCI configuration space read, Win9X/me can use. display data access PCI22 meaning of the norms introduced
exp28_20
- C++程序控制8255(C口输入, A口输出)的直流电机-8255 C program control (C mouth input, output A. I) Motor
exp25_17
- 用c++程序,基于8255和8253实现的一个电子琴程序-with c procedures, based on 8255 and 8253 achieved a flower procedures