资源列表
keyboard__1.1
- 实现数码管输入显示器输出功能（加减乘除运算）-realization of the digital input output function display (arithmetic operations)
shift111
- 本程序实现数字的前向或者后向移动功能，大家可以参考以下-the program prior to the figures, or after moving to function, we can refer to the following
mux16_1
- 本程序实现了对输入数路的16选1功能，需要的同志可以研究研究，共同进步-the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
more111
- 本程序对输入的任意多个二进制数字进行判别（0和1的个数）-procedures for the importation of arbitrary binary figures for the number of discriminant (0 and 1 Number)
12_convert
- convert.vhd 本例是从程序包中提取出来的，不能单独编译-convert.vhd the cases from the package is extracted, not separate compiler
cordic.tar
- cordic程序的VHDL程序源码及说明，有详细的说明，程序有注释-cordic procedures procedures VHDL source code and explanations are detailed explanations, procedures Notes
fcout
- 频率计源代码，性能很好，verilog写的，顶层原理图，底层语言写的，效果很好，开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
16B20B
- 16B20B编码转换，用于高速的串型接口-16B20B encoding conversion for the high-speed serial interface -
usb_2
- usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
canbus_vhdl
- 使用方法： 1.拷贝到硬盘，用ISE打开工程文件即可。-Use : 1. Copy to the hard drive, use ISE project documents can be opened.
cabine
- 3层电梯的控制，利用vhdl写的。运行于maxplus-three-storey elevator control, the use of vhdl writes. Running maxplus
02_SynthesizableMATLAB
- Lab 2 – Synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR