资源列表
zffsq
- 此文是一个完整的字符发生器的设计及设置,文中有完整的vhdl代码及原理图.-This article is a complete character generator design and installation, a complete text of the code and vhdl diagram.
cf_fft_2048v
- 基于FPGA的2048点FFT的verilog实现的源代码。-FPGA-based 2048-point FFT verilog the source code.
programing_voltage_current_resources
- 实现电压\\电流的分别输出,可通过按键选择输出通道.-voltage \\ output current, respectively, through the output channel selection buttons.
maxII16_cpu
- maxII16_cpu,altera的maxII系列的16位cpu-maxII16_cpu, altera the maxII series of 16 cpu
txt_util
- VHDL的字符串处理函数库，含数字与字符串之间的转换-VHDL string handling functions, containing figures and the conversion between the strings
SDRAM_HY57V6416ET
- 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M * * 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
verilog_Divide
- 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
VHDL-I
- VHDL intermediate Level,仅供学习使用-VHDL intermediate Level, is for learning
Odd_Fren
- 一个3分频的VHDL程序,方便学习且仅供学习之用-a frequency of three minutes VHDL procedures, facilitate learning and learning purposes only
VHDL_UART
- VHDL语言的UART串行接口芯片程序,仅供学习使用-VHDL UART serial interface chip procedure is for learning
uart_vhdl_lattice
- UART的rs232通信接口VHDL语言，里面有详细的介绍-UART communication interface rs232 VHDL language, which is described in detail
cmos_FPGA
- 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame