资源列表
AD.FPGA控制AD7321的模块
- FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。,FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.
opb_vga.EDK下的用户IP核
- 一个EDK下的用户IP核，进行OPB总线到VGA的转换,EDK under a user IP core, the OPB bus to VGA conversion
ds18b20.ds18b20的Verilog程序
- ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。,ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.
tlc549.数字电压表的VHDL语言实现
- 数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程,The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD
divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
ASCII-to-HEX.ASCII码转十六进制数
- labview程序：ASCII码转十六进制数，非常实用的程序,labview procedures: ASCII code to hexadecimal number, a very useful procedure
actel FPGA JTAG电路 周立功开发
- actel FPGA JTAG电路 周立功开发 ,actel JTAG
基于DAC0832的示波器显示电路(FPGA)
- 基于DAC0832的示波器显示电路(FPGA),DAC0832 on the oscilloscope display circuit (FPGA)
shift_register.用Verilog实现的移位寄存器
- 用Verilog实现的移位寄存器，可以实现左移、右移等功能,Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
DE2_SD_Card_Audio.DE2上SD卡的读写代码
- DE2上SD卡的读写代码，应用环境quartus ii,DE2 on SD card to read and write code
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
实现USB接口功能的VHDL和verilog完整源代码
- 实现USB接口功能的VHDL和verilog完整源代码,Implementation USB interface functions of the VHDL and Verilog source code integrity