资源列表
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
rom
- verilog 编写的rom代码，开发环境为quartus-rom write verilog code development environment for quartus
electronic_watch
- 电子表仿真，有显示年月日、显示时间、修改年月日、修改时间、闹钟功能-electronic watch. Function: show of data, time, modification of data and time, and set alarm clock.
uart_vhdl
- 串口通讯的VHDL源码，波特率可自行设置，验证通过。-UART VHDL
rs232_VHDL
- RS232 uart的VHDL实现，包括时钟分频（波特率产生），接收，发送-Implement of RS232 uart in VHDL
123654vhaing
- 八音自动播放电子琴设计 vhdl源码，文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play aut
FPGA-for-greenhand
- 本资料适合fpga初学者入门使用，包括：fpga设计资料大全，fpga的交流电机控制，fpga的中文培训教程-This information is suitable for beginners FPGA portal, including: fpga Design Sourcebook, fpga of AC motor control, fpga training course in Chinese
clock
- 用verilog语言实现数字时钟，有注释，规范-Digital clock using verilog language, there are notes, specifications
CORDIC_SINE
- xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
SPI
- 基于FPGA的SPI控制器的设计，有代码和相关文档资料-the design of SPI controlor ,including verilog codes and other documents
SPI
- 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
verilog_sdram
- SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim