资源列表
async_fifo
- 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。（不能直接使用。）-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
pwm_generate_module
- verilog编写的，用按键控制PWM波占空比。可以定义死区，用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
qiangda
- 抢答器，3人进行抢答，即对应三个开关，谁先按下，LED输出显示-Responder, 3 answer, that corresponds to three switches, who first press, LED output display
USB_GPIF-II
- fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量-fpga generate two lane video, and transmit them through GPIF II interface. test cy2014
LED
- 简单的流水灯设计，四个灯轮流闪，测试通过-led test， shift
SIN_COS
- fpga产生正弦波形，sin_cos，modelsim仿真通过-fpga generate sin waveform,test passed
8个数码管显示数码管动态扫描显示
- 共阳极数码管显示1,2,3,4,5,6,7,8。FPGA可直接编译。
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
mux41
- 四选一数据选择器（四个输入选择一个输出）(Four select a data selector)
vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
???
- This is timer code using VHDL