资源列表
time_zh_4
- 按键选择状态，6位数码管显示，有闹钟、整点报时功能，时间可调(Button selection status, 6 digital display, alarm clock, the whole point timekeeping function, time adjustable)
键盘实验文件_modify
- 键盘数据读取，并显示在数码管上，速度可达到100M频率(Read the keyboard data, and display on the digital tube, frequency speed can reach 100M)
zhong5
- Basys2开发板上烧写后，可在LCD1602显示屏上动态显示年月日时分秒和温度值，并且可以手动设置闹钟和温度上下限，越限报警。(Basys2 development board programmer, can dynamically display the date when the minutes and seconds and temperature on the LCD1602 screen, and you can manually set the alarm clock and th
JTAG_Example0_Verilog
- 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
ARM JTAG Debug
- 这篇文章主要介绍 ARM JTAG 调试的基本原理。 基本的内容包括了 TAP (TEST ACCESS PORT) 和 BOUNDARY-SCAN ARCHITECTURE 的介绍， 在此基础上， 结合 ARM7TDMI 详细介绍了的 JTAG 调试原理。(OPEN-JTAG Development Group.)
Lab3
- Use this code to practice zynq library
spi-master
- code for Master side
SPI-Master-master
- Use code for Maser SPI
2015_2_zynq_labdocs_pdf
- These are bocks for Zynq FPGA
eda
- 直接数字频率 相位累加器 寄存器 lpm_rom(Based on VHDL+ FPGA design of the DDS signal has been through mode)
UART
- uart 的verilog源码，希望对大家有用！(UART Verilog source hope useful for all!)
Freq_gen
- XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)