资源列表
pinlvji
- 用4位十进制计数器对用户输入时钟信号进行计数，计数间隔为1秒钟。计数满1秒钟后将计数值（即频率值）所存到4位寄存器中显示，并将计数器清0，在进行下一次计数。 频率计由三种模块组成：testctl为控制模块，由1Hz其准产生rst_cnt,load,cnt_en信号；cnt10为带清0及计数允许的十进制计数器；reg4b为四位寄存器。 -With four decimal counter input clock signal to the user to count, count one
jiaotongdeng
- 用VHDL做的交通灯设计-VHDL to do with the design of the traffic lights
d3dx9_27
- 用vhdl语言实现的乒乓球比赛系统.有计分，裁判，发球等功能。-tabel.vhdl
fq_div
- 一种实现任意整数分频的ＶＨＤＬ源代码，已经经过调试-Achieve an arbitrary integer divider of the VHDL source code, has been testing
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
modelsim
- modelsim入门，简单易学，容易上手。丰富说明-modelsim entry, easy to learn, easy to use. Note the rich
verilog
- vhdl学习资料 清华大学信息学院课件 绝对值得下载-Tsinghua University, studying information vhdl Institute information is worth courseware download
traffic_light
- CPLD控制交通灯程序，很不错的程序！大家一起学习啊！-CPLD to control the traffic light process, the procedure is pretty good! U.S. study with ah!
VHDL
- DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
vga
- 硬件言语编写VGA时序控制，可用FPGA下载检测-vga
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)