资源列表
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
led.control
- Control led with clock
all_bus_20050508.tar
- Vhdl cod for a bus.For sp2e
all_clock_20080928.tar
- Vhdl cod for a clock for sp3e
all_ram_20081116.tar
- vhdl cod for ram.For sp3e
mtd
- MTD定点浮点仿真，可直接用于fpga算法的仿真程序，产生了扫频信号，仿真直接输出系统频率响应函数，为系统测试带来好处-MTD fixed-point floating-point simulation, fpga algorithm can be used directly in the simulation program to produce a sweep signal, the direct simulation output system frequency response fun
modelsim7.2license
- 用于modelsim7.2的破解，里面有详细说明，很有用-For the crack modelsim7.2, which has detailed instructions, very useful
count_free
- 本程序是实现在用电话卡打电话时进行自动计费的功能，包括检测通话的种类，时间和余额检测等多项功能，此代码用veriloghdl编写已经调试通过编译。-Implementation of this procedure is used when the phone card to call the function of automatic billing, including the detection of the types of calls, time and number of functi
quartusII7.2license(2)
- quartus7.2的license破解，里面有详细说明，简单实用-quartus7.2 to break the license, which has detailed descr iption of simple and practical
CodeLock
- 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the syst
ref-sqroot
- 这是用于VHDL的开方运算，大家试试看，能不能好用-sqrt
VHDLexample
- 介绍了VHDL语言实现100列子 内容详细 适合初学者-Introduction of VHDL language Liezi hundred detailed implementation suitable for beginners