资源列表
ds18b20
- ds18b20的介绍及时序，以及对ds18b20进行温度读写的vhdl程序，在quartus环境下进行编译仿真-Introduction ds18b20 and timing, as well as read and write ds18b20 temperature vhdl procedure quartus compiled simulation environment
4
- VHDL 波形发生器VHDL程序与仿真-VHDL Waveform Generator and Simulation of VHDL procedures
edaCourseware
- 本文件中包含有关EDA技术的相关知识，VHDL语言的基本结构和语法-include Courseware about eda
Cymometer_of_four_decimal
- 四位十进制数字频率计： 测量范围：1Hz～10kHz； 显示时间不少于1S； 具有记忆显示的功能，即在测量过程中 刷新数据，等结束后才显示测量结果，给出待测信号的频率值，并保存到下一次测量结束。-Four decimal digital frequency meter: measuring range: 1Hz ~ 10kHz show that no less than 1S with memory function showed that the cour
Verilog
- FPGA 好的开发资料 里面有大量的例子 大家可以多学习学习-it is good information for FPGA
ram_2561
- 这是我自己写的一个小小的VERILOG程序，关于创建一个256个数。-This is what I wrote it myself a little VERILOG procedures, on the creation of a 256 number.
jk_ff
- 这是我自己写的一个关于JK触发器的VERILOG 程序。-This is one I wrote it myself on the JK flip-flop process of VERILOG.
fifo_2
- 一个关于FIFO的VERILOG程序。很不错的。-VERILOG a procedure on the FIFO. Very good.
Multiplier
- 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
counter
- It s a binary counter
cnt_up_down
- It s a counter which count to up, when on the all positions are "1", it count to down
uart
- uart using verilog hdl