资源列表
guard_against_theft
- 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15
bin2bcd
- Binary to BCD converter
testMem
- Example of a FPGA memory controler
EDA
- 用VHDL语言编写的时钟显示的源程序代码-VHDL language used to display the clock source code
Example-b3-1
- ALTER FPGA/GPLD设计（初级篇）的源码，只是其中的一部分供大家参考，如果还有用到其他的，请联系我-ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
lpm_mult0
- 在Quartus2的编程环境下以VHDL语言来实现 32*32 的高速计算-Quartus2 programming environment in the VHDL language under 32* 32 high-speed computing
ADCINT
- 基于VHDL语言的A/D采样控制程序，程序采用状态机实现的-Based on the VHDL language, A/D sampling control procedures, procedures for the use of state machine to achieve the
VHDL_fenpin
- 利用FPGA进行分频期的设计，包括小数，分数等分频-Frequency for the use of FPGA design phase, including the decimal, the frequency scores of sub-
Applicatio_of_VHDL-based_FPGA_design_of_FIR_filter
- VHDL 高速基于分布式滤波器FPGA设计论文-Applicatio_of_VHDL-based_FPGA_design_of_FIR_filters
DDSsinwave
- matlab下，用dspbuilder实现dds模块产生正弦波的源码-matlab under dds with the realization of dspbuilder generated sine wave source modules
rom
- 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
sram64
- 随机存储器VHDL代码，已用quartusII6.0验证，可用，可实现模块-Random access memory VHDL code has been used to verify quartusII6.0 can be used to deliver modules