资源列表
ALU
- 这个是我的数字电路设计报告，利用了vhdl语言制作了一个n位的可配置alu器件，实现了一些基本的功能，附有完整的报告及代码，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-This is my digital circuit design report, using the vhdl language produced an n-bit alu device can be configured to achieve some basic functions, with
Decoder
- the decoder program are used to decode the data for 4:1 decoder using xilinix
encoder
- the encoder are designed to two for switchcase and if else function in verilog
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
signaltapdebugging
- FPGA 逻辑分析仪signaltapII详细用法介绍与调试分析-FPGA signaltapII design and debugging
eth_ocm_80_3
- MAC ethernet ip opencore
system_c_code
- Counter , adder , reset code using system c
bram_test
- Hex file to Binary file conversion using VHDL
round_three_stage
- 3 stage round arbiter using verilog
qpsk_simulink
- Matlab simulink qpsk
speed_test
- QuartusII运行环境下的计数器的VHDL源代码，其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.