资源列表
Xilinx_question
- ：ISE5.1i是Xilinx推出的具有ASIC-strength的设计工具，它充分发掘了VirtexⅡPro系列芯片的潜力；Virtex-II Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比，设计人员在编译时所花的时间得到了成倍提高（从100,000/min增加到200,000门/min）并且在器件速度上增加了40 。-: ISE5.1i is a Xilinx introduced a ASIC-strength design tools, which ful
Command
- sdram控制器命令接口模块的VHDL源程序文件，可直接用-sdam command model
pll1
- sdram控制器pll命令接口模块的VHDL源程序文件，可直接用-sdram pll
sdr_sdram
- sdram控制器顶层模块的VHDL源程序文件，可直接用-sdr SDRAM
ripplelab
- with orgonal frequencey division multiplextinverilog code for ripple carry adder in veriwe- with orgonal frequencey division multiplextinverilog code for ripple carry adder in veriwell
DDS
- 直接数字信号源的源代码和发生器的设计报告-Direct digital signal source code and design report
vhdl
- 10个有关于vhdl例子的程序代码，就是那种带有程序注释的那种-10 on vhdl examples of program code, that is the kind of program notes with the kind of! ! !
FPGAExamples
- A lot of usefull examples on VDHL lenguaje, includes VGA, Mouse, Keyboards, ADC, etc
PWM
- PWM examples in VHDL
VHDL
- 本文是电子工程专辑享有版权的关于可编程逻辑器件应用设计技巧百问，非常实用，希望能帮助您。-This article is copyrighted Electronic Engineering Times on the programmable logic device application design techniques 100 asked, very useful and would like to help you.
jkmk
- 用EDA编的程序 是关于电子钟的很有参考价值-The program is compiled with the EDA on the electronic clock of great reference value to