资源列表
8051_PLJ
- 本设计基于8051IP Core和FPGA技术结合提出一种等精度频率测量方案，解决了传统测频方法测频精度随频率的下降而下降的问题。-The design is based 8051IP Core and FPGA technology combined proposes a precision frequency measurement solutions solve the traditional frequency measurement frequency measurement accu
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
dds_work
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
amb-cui_current_filter1211
- 确实可用的电机用死区控制程序，已验证稳定性-Motor control deadband control
procesador_1
- VHDL project of a small CPU
tutorial1
- Example of VHDL. How to start with VHDL concepts.
EDA-xiti
- 由12进制和60进制计数器组成的时钟电路。-12 229 and 60 binary counter clock circuit.
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
UART-by-Verilog
- 用Verilog实现UART，并且附有详细说明那个-The Verilog UART, and with the detailed descr iption that
dc_rmv
- 这是一个用verilog写的DC滤波器，即melp算法中预处理部分，主要滤除50hz工频干扰，采用一个4阶的切比雪夫高通滤波器，截去频率位60hz以下的信号，其阻带的衰减位30db。-This is a verilog to write a DC filter the preprocessing part that melp algorithm, main filter 50hz frequency interference, the use of a fourth-order Chebyshe
hanzi0430
- 基于FPGA芯片，在16x16的点阵上滚动重复显示多个汉字的源代码-Repeated 16x16 dot matrix rolling display the source code of Chinese characters based on the FPGA chip,
LCD12864
- FPGA控制带字库型12864显示，本程序使用状态机实现状态翻转-The FPGA control with a character type 12864, the program uses state machine state flip