资源列表
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
1
- 进阶实验_01_秒表：数字秒表，按键+数码管-Advanced experimental _01_ stopwatch: digital stopwatch, digital keys+
uart
- 以电原理图为顶层， 设计一个异步通信接收器，波特率为19200，接收的数据为学号，并在开发板上用数码管显示。-Electrical Schematic diagram for the top layer, design an asynchronous communication receivers,the baud rate is 19200, the received data is the student numbers,display it using the digital tube.
clock_counter
- 数字时钟，可以调时，整点可以鸣叫，功能齐全，代码简洁。-Digital clock, you can tune the whole point of call and full-featured, simple code.
chuan2
- 用verilog HDL编写的并串转换模块，在ISE软件仿真过，也可综合-Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
[FPGA]Capacitor_tester_on_CyclonEP1C3T144C8N
- 在Cyclon EP1C3T144C8N上实现的电容表 自己亲手设计制作验证过，附有详细的文档。 -A capacitor tester with a scale 1nF～9999uF.
control
- 该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。-This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.
labassin1
- assignment in verilog 3
temperature
- 温度传感器实验，将温控芯片的温度信号通过fpga用数码管显示-temperature display
m7000
- m7000是FPGA的一种主要的芯片，该文比较适合初学者阅读-m7000
m7000
- ALTERA MAX EPM7000 series CPLD full datasheet